Thermal and IR Drop Analysis Using Convolutional Encoder-Decoder Networks

Vidya A. Chhabria; Vipul Ahuja; Ashwath Prabhu; Nikhil Patil; Palkesh Jain; Sachin S. Sapatnekar

doi:10.1145/3394885.3431583

Thermal and IR Drop Analysis Using Convolutional Encoder-Decoder Networks

Vidya A. Chhabria, Vipul Ahuja, Ashwath Prabhu, Nikhil Patil, Palkesh Jain, Sachin S. Sapatnekar

Electrical and Computer Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

21 Scopus citations

Abstract

Computationally expensive temperature and power grid analyses are required during the design cycle to guide IC design. This paper employs encoder-decoder based generative (EDGe) networks to map these analyses to fast and accurate image-to-image and sequence-to-sequence translation tasks. The network takes a power map as input and outputs the temperature or IR drop map. We propose two networks: (i) ThermEDGe: a static and dynamic full-chip temperature estimator and (ii) IREDGe: a full-chip static IR drop predictor based on input power, power grid distribution, and power pad distribution patterns. The models are design-independent and must be trained just once for a particular technology and packaging solution. ThermEDGe and IREDGe are demonstrated to rapidly predict on-chip temperature and IR drop contours in milliseconds (in contrast with commercial tools that require several hours or more) and provide an average error of 0.6% and 0.008% respectively.

Original language	English (US)
Title of host publication	Proceedings of the 26th Asia and South Pacific Design Automation Conference, ASP-DAC 2021
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	690-696
Number of pages	7
ISBN (Electronic)	9781450379991
DOIs	https://doi.org/10.1145/3394885.3431583
State	Published - Jan 18 2021
Event	26th Asia and South Pacific Design Automation Conference, ASP-DAC 2021 - Virtual, Online, Japan Duration: Jan 18 2021 → Jan 21 2021

Publication series

Name	Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Conference

Conference	26th Asia and South Pacific Design Automation Conference, ASP-DAC 2021
Country/Territory	Japan
City	Virtual, Online
Period	1/18/21 → 1/21/21

Bibliographical note

Funding Information:
This work is supported in part by the DARPA IDEA program as a part of the OpenROAD project.

Publisher Copyright:
© 2021 Association for Computing Machinery.

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Chhabria, V. A., Ahuja, V., Prabhu, A., Patil, N., Jain, P., & Sapatnekar, S. S. (2021). Thermal and IR Drop Analysis Using Convolutional Encoder-Decoder Networks. In Proceedings of the 26th Asia and South Pacific Design Automation Conference, ASP-DAC 2021 (pp. 690-696). Article 3431583 (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1145/3394885.3431583

Thermal and IR Drop Analysis Using Convolutional Encoder-Decoder Networks. / Chhabria, Vidya A.; Ahuja, Vipul; Prabhu, Ashwath et al.
Proceedings of the 26th Asia and South Pacific Design Automation Conference, ASP-DAC 2021. Institute of Electrical and Electronics Engineers Inc., 2021. p. 690-696 3431583 (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Chhabria, VA, Ahuja, V, Prabhu, A, Patil, N, Jain, P & Sapatnekar, SS 2021, Thermal and IR Drop Analysis Using Convolutional Encoder-Decoder Networks. in Proceedings of the 26th Asia and South Pacific Design Automation Conference, ASP-DAC 2021., 3431583, Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, Institute of Electrical and Electronics Engineers Inc., pp. 690-696, 26th Asia and South Pacific Design Automation Conference, ASP-DAC 2021, Virtual, Online, Japan, 1/18/21. https://doi.org/10.1145/3394885.3431583

Chhabria VA, Ahuja V, Prabhu A, Patil N, Jain P, Sapatnekar SS. Thermal and IR Drop Analysis Using Convolutional Encoder-Decoder Networks. In Proceedings of the 26th Asia and South Pacific Design Automation Conference, ASP-DAC 2021. Institute of Electrical and Electronics Engineers Inc. 2021. p. 690-696. 3431583. (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC). doi: 10.1145/3394885.3431583

Chhabria, Vidya A. ; Ahuja, Vipul ; Prabhu, Ashwath et al. / Thermal and IR Drop Analysis Using Convolutional Encoder-Decoder Networks. Proceedings of the 26th Asia and South Pacific Design Automation Conference, ASP-DAC 2021. Institute of Electrical and Electronics Engineers Inc., 2021. pp. 690-696 (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC).

@inproceedings{a8754d4cb0d64238afc48e095ebae6e8,

title = "Thermal and IR Drop Analysis Using Convolutional Encoder-Decoder Networks",

abstract = "Computationally expensive temperature and power grid analyses are required during the design cycle to guide IC design. This paper employs encoder-decoder based generative (EDGe) networks to map these analyses to fast and accurate image-to-image and sequence-to-sequence translation tasks. The network takes a power map as input and outputs the temperature or IR drop map. We propose two networks: (i) ThermEDGe: a static and dynamic full-chip temperature estimator and (ii) IREDGe: a full-chip static IR drop predictor based on input power, power grid distribution, and power pad distribution patterns. The models are design-independent and must be trained just once for a particular technology and packaging solution. ThermEDGe and IREDGe are demonstrated to rapidly predict on-chip temperature and IR drop contours in milliseconds (in contrast with commercial tools that require several hours or more) and provide an average error of 0.6% and 0.008% respectively.",

author = "Chhabria, {Vidya A.} and Vipul Ahuja and Ashwath Prabhu and Nikhil Patil and Palkesh Jain and Sapatnekar, {Sachin S.}",

note = "Funding Information: This work is supported in part by the DARPA IDEA program as a part of the OpenROAD project. Publisher Copyright: {\textcopyright} 2021 Association for Computing Machinery.; 26th Asia and South Pacific Design Automation Conference, ASP-DAC 2021 ; Conference date: 18-01-2021 Through 21-01-2021",

year = "2021",

month = jan,

day = "18",

doi = "10.1145/3394885.3431583",

language = "English (US)",

series = "Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "690--696",

booktitle = "Proceedings of the 26th Asia and South Pacific Design Automation Conference, ASP-DAC 2021",

}

TY - GEN

T1 - Thermal and IR Drop Analysis Using Convolutional Encoder-Decoder Networks

AU - Chhabria, Vidya A.

AU - Ahuja, Vipul

AU - Prabhu, Ashwath

AU - Patil, Nikhil

AU - Jain, Palkesh

AU - Sapatnekar, Sachin S.

PY - 2021/1/18

Y1 - 2021/1/18

N2 - Computationally expensive temperature and power grid analyses are required during the design cycle to guide IC design. This paper employs encoder-decoder based generative (EDGe) networks to map these analyses to fast and accurate image-to-image and sequence-to-sequence translation tasks. The network takes a power map as input and outputs the temperature or IR drop map. We propose two networks: (i) ThermEDGe: a static and dynamic full-chip temperature estimator and (ii) IREDGe: a full-chip static IR drop predictor based on input power, power grid distribution, and power pad distribution patterns. The models are design-independent and must be trained just once for a particular technology and packaging solution. ThermEDGe and IREDGe are demonstrated to rapidly predict on-chip temperature and IR drop contours in milliseconds (in contrast with commercial tools that require several hours or more) and provide an average error of 0.6% and 0.008% respectively.

AB - Computationally expensive temperature and power grid analyses are required during the design cycle to guide IC design. This paper employs encoder-decoder based generative (EDGe) networks to map these analyses to fast and accurate image-to-image and sequence-to-sequence translation tasks. The network takes a power map as input and outputs the temperature or IR drop map. We propose two networks: (i) ThermEDGe: a static and dynamic full-chip temperature estimator and (ii) IREDGe: a full-chip static IR drop predictor based on input power, power grid distribution, and power pad distribution patterns. The models are design-independent and must be trained just once for a particular technology and packaging solution. ThermEDGe and IREDGe are demonstrated to rapidly predict on-chip temperature and IR drop contours in milliseconds (in contrast with commercial tools that require several hours or more) and provide an average error of 0.6% and 0.008% respectively.

UR - http://www.scopus.com/inward/record.url?scp=85100521742&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85100521742&partnerID=8YFLogxK

U2 - 10.1145/3394885.3431583

DO - 10.1145/3394885.3431583

M3 - Conference contribution

AN - SCOPUS:85100521742

T3 - Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

SP - 690

EP - 696

BT - Proceedings of the 26th Asia and South Pacific Design Automation Conference, ASP-DAC 2021

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 26th Asia and South Pacific Design Automation Conference, ASP-DAC 2021

Y2 - 18 January 2021 through 21 January 2021

ER -

Thermal and IR Drop Analysis Using Convolutional Encoder-Decoder Networks

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