TY - GEN
T1 - Understanding the impact of transistor-level BTI variability
AU - Fang, Jianxin
AU - Sapatnekar, Sachin S.
PY - 2012
Y1 - 2012
N2 - Recent work has shown large variations due to bias-temperature instability (BTI) at the device level, and we study its impact on the behavior of larger circuits. We propose an analytical method that is over 600x faster than Monte Carlo simulation and accurate for technologies down to 16nm, and demonstrate it on circuits with up to 68,000 transistors. Results show that the impact of BTI variability at the circuit level is significantly smaller than at the device level, but increases with device downscaling.
AB - Recent work has shown large variations due to bias-temperature instability (BTI) at the device level, and we study its impact on the behavior of larger circuits. We propose an analytical method that is over 600x faster than Monte Carlo simulation and accurate for technologies down to 16nm, and demonstrate it on circuits with up to 68,000 transistors. Results show that the impact of BTI variability at the circuit level is significantly smaller than at the device level, but increases with device downscaling.
KW - Bias-Temperature Instability (BTI)
KW - Degradation Analysis
KW - Digital Circuit Delay
KW - Variability
UR - http://www.scopus.com/inward/record.url?scp=84866628787&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84866628787&partnerID=8YFLogxK
U2 - 10.1109/IRPS.2012.6241887
DO - 10.1109/IRPS.2012.6241887
M3 - Conference contribution
AN - SCOPUS:84866628787
SN - 9781457716799
T3 - IEEE International Reliability Physics Symposium Proceedings
SP - CR.2.1-CR.2.6
BT - 2012 IEEE International Reliability Physics Symposium, IRPS 2012
T2 - 2012 IEEE International Reliability Physics Symposium, IRPS 2012
Y2 - 15 April 2012 through 19 April 2012
ER -