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A 23.5GHz PLL with an adaptively biased VCO in 32nm SOI-CMOS
J. O. Plouchart, M. Ferriss, A. Natarajan, A. Valdes-Garcia, B. Sadhu, A. Rylyakov, B. Parker, M. Beakes, A. Babakani, S. Yaldiz, L. Pileggi, Ramesh Harjani, S. Reynolds, J. A. Tierno, D. Friedman
Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
6
Scopus
citations