TY - GEN

T1 - Unified algorithm for gate sizing and clock skew optimization to minimize sequential circuit area

AU - Chuang, Weitong

AU - Sapatnekar, Sachin S.

AU - Hajj, Ibrahim N.

PY - 1993/12/1

Y1 - 1993/12/1

N2 - This paper examines the problem of minimizing the area of a synchronous sequential circuit for a given clock period specification under the standard-cell paradigm. This is effected by appropriately selecting a size for each gate in the circuit from a standard-cell library, and by adjusting the delays between the central clock distribution node and individual flip-flops. Traditional methods treat these two problems separately, which may lead to very sub-optimal solutions in some cases. Experimental results show that by considering the two problems together, it is not only possible to reduce the optimized circuit area, but also to achieve faster clocking frequencies. We also address the problem of making this work applicable to very large synchronous sequential circuits by partitioning these circuits to reduce the computational complexity.

AB - This paper examines the problem of minimizing the area of a synchronous sequential circuit for a given clock period specification under the standard-cell paradigm. This is effected by appropriately selecting a size for each gate in the circuit from a standard-cell library, and by adjusting the delays between the central clock distribution node and individual flip-flops. Traditional methods treat these two problems separately, which may lead to very sub-optimal solutions in some cases. Experimental results show that by considering the two problems together, it is not only possible to reduce the optimized circuit area, but also to achieve faster clocking frequencies. We also address the problem of making this work applicable to very large synchronous sequential circuits by partitioning these circuits to reduce the computational complexity.

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M3 - Conference contribution

AN - SCOPUS:0027839526

SN - 0818644923

T3 - Proc 1993 IEEE ACM Int Conf Comput Aided Des

SP - 220

EP - 223

BT - Proc 1993 IEEE ACM Int Conf Comput Aided Des

A2 - Anon, null

PB - Publ by IEEE

T2 - Proceedings of the 1993 IEEE/ACM International Conference on Computer-Aided Design

Y2 - 7 November 1993 through 11 November 1993

ER -